Tag Archives: CPU

Cosino Enigma is an SAMA5D3 based CPU module

How the secure boot works

Enigma’s CPU has two way of functioning: normal mode and secure mode. In the former mode, the CPU is no different than all other CPUs; however, once the secure mode is activated, it will execute ONLY encrypted code.

In normal mode, the boot stages consist of:

The on-chip ROM bootloader loads the pre-bootloader from an external mass storage into the internal RAM, then
The pre-bootloader sets up the external RAM and loads the bootloader from an external mass storage into external RAM, then
The bootloader can setup some peripherals in order to prepare the system for the kernel and loads the kernel from an external mass storage into external RAM, then
The kernel activates all system’s peripherals and mounts the rootfs from an external mass storage and starts the user’s processes executions.

Starting from stage 2, all the software that is not coded in ROM can be potentially subjected to attempts to replace the original firmware with a malicious one, simply by altering the code images stored into the system’s mass storage memory.

In industry applications this can lead to several issues related to system security. For instance, let’s consider a biomedical application where the system MUST not work continuously for more than 2 hours. The manufacturer can program the software in order to respect this directive; however, a malicious user may gain access to the system’s mass storage, copy it and then modify it in such a way that the machine can now work for more than 2 hours!

How can the manufacturer protect itself? It can simply use the secure mode!

Once the secure mode is activated, the Enigma’s CPU will execute ONLY encrypted code. In fact, when in secure mode, the internal ROM boot loader (during stage 1), will load the pre-bootloader image and it will then decrypt it by using the AES algorithm with the secret key deeply stored into the CPU.

Note that the AES key is not readable by using any CPU instruction nor the JTAG which is disabled too!

It’s obvious that without knowing the secret key is quite difficult to alter the pre-bootloader code! While, we have just shown that the second stage is secure, by using the same trick for both stage 3 and 4, all the booting chain is secure as well.

But, what about the root file system? Several solutions may be used; however, the SAMA5D3 based Cosino Enigma solution is used as an embedded file system into the kernel, and in the event that large data storage is needed, to mount an encrypted partition.

What the secure boot cannot do

Despite the secure mode, your system is not protected against backdoors and programming bugs, but these issues are NOT due the secure mode but due weak programmers! The secure mode can assure that your code cannot be altered and/or read so, if your code is well-written, the system is strongly protected against malicious attacks.

The secure boot and the Libre Software

Since Cosino Enigma runs a complete GNU/Linux system, how can it fit within the open source/free software licences? The answer: the unlock track.

By damaging this track on the board, the user can unlock the system; that is, even in secure mode the CPU can run unencrypted code, so every open source/free software licence is respected! Of course, the manufacturer can release the open source/free software code but NOT its protected code.

In addition, the integrity of the unlock track can be used to assert the warranty integrity; once damaged, the unlock path can assert that the warranty is now void. The open source/free software licence is saved and the manufacturer can decline all responsibility against any software modifications.

Hardware overview

The newly-unveiled board features a vast range of I/O peripherals and communication ports. Along with the TFT touchscreen LCD panels driver capable of resolutions up to 1024×768 pixels, it makes the Cosino Engima quite suitable for human/machine interfaces, gateways, and industrial controllers.

Aside from the ARM Cortex-A5 based SAMA5D3, other key specs include:

Internal hardware floating-point unit
256MB (optional 512) SDRAM DDR2
256MB NAND
1x Ethernet 10/100 (optional 1000)
2x USB Host 2.0
1x USB Host/Device 2.0
2x microSD
7x UART
1x LCD
1x real-time clock1
1x I2C
2x SPI
1x crypto engine
1x true number generator

Interested in learning more? You can check out Cosino’s official page here.

ATmega328P + ARM Cortex-A7 = Akarel

A PIR motion activated camera with Atmel & ARM

32-bit AVR MCUs for automotive applications (Part 2)

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In the first part of this series, we took a closer look at how Atmel’s AVR low-power 32-bit microcontrollers (MCUs) help enable the implementation of various product-differentiating features, including advanced control algorithms, voice control and capacitive touch sensing.

We also discussed powering Atmel’s AVR UC3C 32-bit automotive-grade microcontrollers with either a 3.3V or a 5V supply (generally supporting 5V I/O). This has been achieved by moving to a modified 0.18-micron process technology, which supports higher I/O voltage levels in a reliable and cost-effective manner without any complex and expensive voltage conversion. In addition to supporting 5V I/O, the UC3C has been designed to support a wide range of high-performance peripherals required by automotive applications, including:

ADC: 16 channels with 12-bit resolution at up to 1.5M samples/second; dual sample and hold capabilities; built-in calibration; internal and external reference voltages.
DAC: Four outputs (2 x 2 channels) with 12-bit resolution; up to 1M sample/second conversion rate with 1us settling time; flexible conversion range; one continuous or two sample/hold outputs per channel.
Analog comparator: Four channels with selectable power vs. speed; selectable hysteresis (0.20mV and 50mV); flexible input selections and interrupts; window compare function by combining two comparators.
Timer/Counter: multiple clock sources (five internal and three external); rich feature set (counter, capture, up/down, PWM); two input/output signals per channel; global start control for synchronized operation.
Quadrature decoder: Integrated decoder supports direct motor rotation detection.
Multiple interfaces: includes a two-channel, two-wire interface (TWI), master/slave SPI, and full-featured USART that can be used as an SPI or LIN.
Fully integrated USB: built-in USB 2.0 transceivers support low (1.5Mbps), full (12Mbps) and on-the-go modes; included in the AVR Software Framework are production-ready drivers for various USB devices (mass storage, HID, CDC, audio), hosts (mass storage, HID, CDC) and combined function devices.

Atmel’s AVR UC3C 32-bit automotive-grade microcontrollers are also designed to achieve higher system throughput with our Peripheral Event System.

“Managing peripherals by the CPU can become a major system bottleneck, especially as the number of peripherals and their operating frequencies increase. With high sampling rates across multiple channels, interrupt overhead and data processing can consume a large percentage of the processor’s available clock cycles,” an Atmel engineering rep told Bits & Pieces. “If the CPU load needs to manage a single SPI port even at a low data rate of 1.2Mbps, this would require 53% of the processor’s capacity. In addition, the interrupt latency increases and introduces jitter.”

And that is why AVR UC3C architecture utilizes Atmel’s peripheral event system, which allows CPU-independent handling of inter-peripheral signaling through an internal communication fabric that interconnects all peripherals. Rather than triggering an interrupt to tell the CPU to read a peripheral or port, the peripheral instead manages itself by directly transferring data to the SRAM for storage – all without requiring any action by the CPU.

“From a power perspective, only those blocks that are part of the conversion are active. The CPU is free to execute application code or conserve power in idle mode during the entire event,” the Atmel engineering rep continued. “In addition, the peripheral event controller allows a more deterministic response compared to a CPU-based, interruptdriven event controller, because the latency is fixed to 3 cycles, i.e., 33ns when operating at 66MHz. This enables precise timing of events without jitter, resulting in constant sample rates for ADCs and DACs.”

Interested in learning more about 32-bit AVR MCUs for automotive applications? Be sure to check out part three of this series which details how Atmel MCUs can be used to help protect IP and bolster system safety. Interested in learning more about 32-bit AVR MCUs for automotive applications? Be sure to check out part one, two, three and four of this series.

ATmega256RFR2 powers low-cost Ethernet to wireless gateways: Part 1

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Atmel’s low-cost gateway (LCGW) reference design – powered by the ATmega256RFR2 – is a turn-key production-ready solution that connects IEEE 802.15.4 wireless networks to wired Ethernet networks. This gateway allows IEEE 802.15.4 wireless devices to link with mobile devices such as smartphones and tablets running remote-control applications.

“The ATmega256RFR2 wireless system-on-a-chip (SoC) combines best-in-class radio performance with the efficient Atmel AVR 8-bit CPU,” an Atmel engineering rep told Bits & Pieces. “In short, the ATmega256RFR2 provides a responsive CPU and high-performance radio to address the demanding tasks of network coordinator and data concentrator.”

Meanwhile, the WIZnet W5200 embedded Ethernet controller features a 10BaseT/100BaseTX MAC and PHY, supporting numerous popular Ethernet protocols including TCP/IP, UDP and IPv4.

“Essentially, the wired Ethernet interface is a low-cost, reliable and secure connection that works with the end user’s existing routers, access-points, WLANs and ISPs,” the engineering rep continued. “Remember, wired Ethernet lowers cost and also avoids interference problems and regulatory issues inherent with co-located radio solutions.”

The engineering rep also noted that the reference design was formulated with low BOM cost as a primary objective. As such, the design is free of superfluous accessories and non-essential sub-systems, with a standard JTAG interface provided for programming and debug.

Atmel’s design includes optional EEPROM and Data-Flash memory sockets, while DC power is derived from a USB Micro-B Dedicated Charge Port (DCP) – allowing users to power the gateway with common phone chargers or from Wi-Fi Access Points via USB ports. As expected, both the USB and Ethernet connections have ESD/EMI suppression to improve reliability.

In terms of operation, connections to the LCGW are relatively simple. Connect the DCP to a USB power source using the Micro-B connector and D3 will light indicating DC power is ready. Then, connect the RJ45 Ethernet port to a router with a CAT5 patch cable.

“Atmel’s ATmega256RFR2 can be programmed and debugged using the 10-pin JTAG header and Atmel JTAGICE programmers. SW2 is a hardware RESET for the CPU, while Ethernet MAC Reset is driven by software,” the engineering rep explained. “And J5 exposes the power rails for testing. There are several user defined features: UART0, Port F GPIO, SW1 and D1 are uncommitted and available to the application developer.”

On the CPU side, Atmel’s ATmega256RFR2 is a low-power CMOS 8-bit microcontroller based on AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4GHz ISM band. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing system designers to optimize power consumption versus processing speed. Meanwhile, the radio transceiver provides high data rates from 250kb/s up to 2Mb/s, frame handling, outstanding receiver sensitivity and high transmit output power enabling a very robust wireless communication.

Interested in learning more about Atmel’s low-cost gateway reference design? Be sure to check back tomorrow for part two of our in-depth look at the ATmega256RFR2-powered LCGW.

Low-power design in the age of IoT

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Facilitating low-power designs for electronic devices is more important than ever before as we move toward a world dominated by the Internet of Things (IoT).

Essentially, the IoT refers a future scenario in which all types of electronic devices link to each other via the Internet. Today, it’s estimated that there are nearly 10 billion devices in the world connected to the Internet, a figure expected to triple to nearly 30 billion by 2020.

The challenge? Reducing power consumption (to extend battery life) while simultaneously maintaining acceptable levels of performance. Fortunately, Atmel has been focusing on low power consumption for more than ten years across its extensive portfolio of AVR and ARM-based microcontrollers and embedded microprocessors.

Design techniques employed to achieve the critical balance between power consumption and performance include:

Use of hardware DMA and event system to offload the CPU
Cut clock or supply on device portions not in use
Careful balance of high performance and low leakage transistors
Fast wake up from low power modes
Low voltage operation

“With the Atmel picoPower technology found in our AVR 8-bit and 32-bit microcontrollers, we’ve even gone one step further. All picoPower devices are designed from the ground up for lowest possible power consumption – all the way from transistor design and process geometry, to sleepmodes and flexible clocking options,” an Atmel engineering rep told Bits & Pieces.

“Atmel picoPower devices can operate down to 1.62V while still maintaining all functionality, including analog functions. They have short wake-up time, with multiple wake-up sources from even the deepest sleep modes.”

Although certain elements of picoPower tech cannot be directly configured by the user, they do form a solid base that facilitates ultra-low-power application development without compromising functionality. On the user level, flexible and powerful features and peripherals allow engineers to more easily apply a wide range of techniques to reduce a system’s total power consumption even further. As expected, picoPower technology is also relatively simple to deploy, with both basic and advanced techniques reducing the power consumption of an application even further.

A perfect example of Atmel’s commitment to low-power devices is the 0.7V tinyAVR. Remember, a typical microcontroller requires at least 1.8V to operate – while the voltage of a single battery-cell ranges from 1.2V to 1.5V when fully charged, dropping gradually below 1V during use (yet still holding a reasonable amount of charge). This means the average microcontroller requires at least two battery cells.

“We have solved this problem by integrating a boost converter inside the ATtiny43U, converting a DC voltage to a higher level and bridging the gap between minimum supply voltage of the microcontroller and the typical output voltages of a standard single cell battery,” the Atmel engineering rep explained. “The boost converter provides the microcontroller with a fixed supply voltage of 3.0V from a single battery cell even when the battery voltage drops down to 0.7V.”

Simply put, this extends battery life by allowing non-rechargeable batteries to be drained to the minimum, while programmable shut-off levels above the critical minimum voltage level avoid damaging the battery cell of rechargeable batteries.

Interested in learning more about Atmel’s low-power, high performance portfolio? Be sure to check out our extensive ARM and AVR product lineups here.

Atmel’s AVR UC3: Low power & ease of use

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Atmel’s AVR UC3 has popped up in quite a number of use recent cases on Bits & Pieces, so today we will be taking a closer look at the stalwart microcontroller (MCU) family which is built on high-performance 32-bit AVR architecture and optimized for highly integrated applications.

Essentially, the AVR UC3 delivers high computational throughput, deterministic real-time control, low-power consumption, low system cost, high reliability and ease-of-use. As previously discussed on Bits & Pieces, the AVR CPU boasts a plethora of cutting-edge features including integer and fixed point DSP (digital signal processor) arithmetic and single-cycle multiply-accumulate instructions.

Meanwhile, a dual-port SRAM, peripheral DMA (direct memory access) controller and multi-layer, high-speed bus architecture makes the AVR UC3 core ideal for high-throughput applications. As such, AVR UC3 devices are perfectly suited for portable and battery-powered applications due to their optimized low-power properties.

Another important feature of Atmel’s AVR UC3 is picoPower technology, which allows the AVR UC3 to further extend the battery life of portable devices.

“True 1.62V operation means selected AVR UC3 devices can utilize a 1.8V (± 10%) regulated power supply – with all functions working,” an Atmel engineering rep told Bits & Pieces. “Indeed, picoPower AVR UC3 devices consume only 650nA with the RTC (real time clock) running, enabling ultra-low sleep current combined with fast wake-up for high integrated microcontrollers.”

On the security side, selected AVR UC3 devices provide mechanisms to protect the system from unauthorized modification, flash software theft and runaway code. Atmel’s FlashVault code protection allows CPU resources and sections of code/data memory to be reserved for proprietary software IP or critical sections of code/data, while a special API (application programming interface) is used to access these resources from the rest of the code. Attempts to access these resources by circumventing this API (either by hacking or runaway code) will be aborted and result in an exception.

In terms of the Digital Signal Processor, the 32-bit AVR UC3 offers unrivaled DSP performance compared to legacy architectures.

“By including powerful instructions for single cycle, multiply accumulate and fractional multiply for various number formats, the 32-bit AVR UC3 delivers unrivaled DSP (digital signal processor) performance compared to legacy architectures,” the Atmel engineering rep noted. “In the AVR UC3 software framework more than 70 DSP functions have been assembly optimized utilizing these instructions. In short, DSP has never been easier.”

And last, but certainly not least, Atmel’s peripheral DMA (direct memory access) controller sets a new standard for data transfer efficiency. For example, if the peripheral DMA controller is not enabled, the maximum usable transfer rate on the SPI (serial peripheral interface) module would be approximately 1MBit/s – occupying the CPU with more than 50% load just moving data around. However, with the peripheral DMA controller, this bottleneck is removed and the Atmel AVR UC3 microcontroller can achieve a transfer rate of 33MBit/s on SPI and USART with only a 15% load on the CPU.

“The innovative peripheral event system in the AVR UC3 also represents a paradigm shift, as it allows the AVR UC3 to send signals (events) directly to other peripherals without involving the CPU. This ensures short and predictable response time. At the same time it offloads the CPU and reduces power consumption,” the engineering rep added.

Want to learn more about Atmel’s lineup AVR UC3 MCUs? Be sure to check out our official UC3 page here.

A closer look at Atmel’s Peripheral Event System

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As previously discussed on Bits & Pieces, Atmel recently introduced the SAM D20 MCU, an extensive product lineup based on ARM’s Cortex -M0+.

The SAM D20 boasts a number of power-saving techniques, including an event system that allows peripherals to communicate directly with each other without involving the CPU or bus resources. This is known as the Peripheral Event System.

According to Andreas Eieland, Sr. Product Marketing Manager at Atmel, the Peripheral Event System can best be described as a routing network independent of the traditional data bus paths. Meaning, different triggers at the peripheral level can result in an event, like a timer tick triggering a reaction in another peripheral.

“Comprising 8 independent channels, the Event System offers a fixed latency of 2 cycles. Without any jitter it is a 100% deterministic method and a perfect fit for real-time applications,” Eieland explained.

“No events are lost and they are handled at a peripheral level in two cycles, even if the CPU is performing a non maskable interrupt. Traditionally the way of handling actions for a low power application would be through the use of interrupts, although they wake up the CPU.”

To better illustrate the advantages of an Event System, Eieland cited an example of a motor drive application using PWM.

“To detect erroneous situations, many motor applications use an analog comparator or ADC to measure the current going into the motor drive, in an over current situation you want to shut down the PWM channels driving the motor as soon as you can to prevent permanent damage to the circuit and for safety reasons,” he said.

“Without an Event System the overcurrent situation will trigger an interrupt, but the interrupt service request might be delayed if the CPU is performing other higher priority tasks. Using the Event System you can connect the analog comparator or ADC directly to the timer and always shut down the timer in two cycles, regardless of what the rest of the MCU is doing.”

Although Peripheral Event capabilities are useful on many different levels, the primary advantages of such a feature include minimizing power consumption, optimizing the off-loading of routine tasks from the CPU and achieving a totally predictable reaction time.

Additional information about Atmel’s Peripheral Event System can be found here.

Getting up close and personal with Atmel’s tinyAVR

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So Atmel’s tinyAVR tech has been in the news lately, popping up in the Agent smart watch which recently debuted on Kickstarter and the uber-cool ShuttAVR mod for cameras.

As previously reported on Bits & Pieces, the Agent smart watch combines the SAM4S and tinyAVR MCUs to provide extended battery life – consuming less than half the power of competing platforms. Essentially, the tinyAVR MCU handles maintenance tasks and events while the ARM-based SAM4S deals with the operating system and related apps. This combination optimizes power use and enables the larger SAM4S microcontroller to remain in sleep mode for as long as possible.

Meanwhile, “balthamos89” used the versatile AVR ATtiny25 to help build the ShuttAVR, a device which allows cameras to snap pictures at precisely defined intervals.

“I happened to have some AVR ATtiny25′s lying around, so I popped open the IR remote for the camera and poked around a bit. Though, I poked around a bit too much and ended up with a broken IR remote,” he explained.

“Determined, I ripped out the old chip and soldered a new switch. I had to add in code for handling the IR signaling, but I ended up with a functioning remote. Not only that, but it had intervalometer capabilities as well.”

So let’s take a closer look at Atmel’s tinyAVR technology which resides under the hood of a growing number of cool devices these days.

First off, all tinyAVRs are based on the same architecture and compatible with other AVR devices. Features like integrated ADC, EEPROM memory and brownout detectors allow users to design applications without adding external components. tinyaAVR also offers up flash memory and on-chip debug for fast, secure, cost-effective in-circuit upgrades.

“The tinyAVR offers an advanced combination of miniaturization, processing power, analog performance and system-level integration,” an Atmel engineer explained. “Simply put, the tinyAVR is the most compact device in the AVR family and the only device capable of operating at just 0.7V. And there’s nothing really tiny about that. Plus, tinyAVR designs can be coupled with Atmel’s CryptoAuthentication tech for an extra level of security against hackers and cloners.”

It should also be noted that the smallest tinyAVR measures only 1.5mm x 1.4mm. This means makers, modders and engineers can all employ the tinyAVR as a single chip solution in small systems – or use it to deliver glue logic and distributed intelligence in larger systems.

“The AVR CPU gives the tinyAVR devices the same high performance as our larger AVR devices,” the engineer continued. “Flexible and versatile, they feature high code efficiency that lets them fit a broad range of applications.”

As expected, tinyAVR offers a high level of integration, with each ping boasting multiple uses as I/O, ADC, and PWM. To be sure, even the reset pin can be reconfigured as an I/O pin. Oh, and yes, the tinyAVR also features a Universal Serial Interface (USI) which can be used as SPI, UART or TWI.

On the power side, where most microcontrollers require 1.8V or more to operate, the tinyAVR boosts the voltage from a single AA or AAA battery into a stable 3V supply to power an entire application.

So if you do use tinyAVR tech in your next maker, hacked, modded or industrial project, be sure to drop us a line and let us know! In the meantime, additional information about Atmel’s extensive tinyAVR lineup can be be found here.

SleepWalking Helps Conserve Energy

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Imagine you are the sole care-provider for a household full of babies all under the age of 3. Each and every single one of them requires you to tend their needs and desires. From feeding to going to the bathroom, from burping to changing their diapers, from bathing to putting them to nap/sleep to keeping them entertained, you are needed every single step of the way. Isn’t that just exhausting? Fast forward by a decade when they are grow to become teenagers – autonomy and self-sufficiency – in which they can all satisfy their own basic needs without your help, unless it’s an urgent matter. Now you have much more free time to read a book, surf the net, get a job, or take a nap.

In essence, this is what SleepWalking is all about in the realm of an Atmel MCU. Traditionally a technology found in the AVR architecture only, it is now incorporated into the ARM architecture as well. It is a feature that extends the concept of autonomous peripherals (babies) that operate independently of the CPU core (a parent or care-provider) during active mode, to actually keeping the peripherals functional when the system clock has been stopped. This is achieved by clocking the peripherals using the real‐time clock (RTC), instead of the system clock.

In the SAM4L, SleepWalking has been integrated into many of the peripherals, including the analog comparator, the ADC, the I2C, UART and the capacitive touch interface. It is then the peripheral that decides whether to wake the system, instead of the CPU waking periodically to carry out an interrupt service routine. With this feature, the need to wake the CPU reduces significantly thus allowing it to stay inactive for longer and more frequent and thereby conserving more energy.

For more information, check out this video for a more detailed explanation on SleepWalking. Please note: despite the AVR UC3 being used as an example in the video, the underlying fundamentals of how SleepWalking works and its benefits are the same as in the ARM SAM4L.

How the secure boot works

What the secure boot cannot do

The secure boot and the Libre Software

Hardware overview

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