Tag Archives: advanced Harvard architecture

A closer look at Atmel’s AVR CPU

Atmel’s 8- and 32-bit AVR CPUs are based on advanced Harvard architecture – which is perhaps best known for neatly balancing power consumption with performance.

Like every Harvard architecture device, the AVR CPU is equipped with two busses: one instruction bus where the CPU reads executable instructions; and a second data bus to read or write the corresponding data.

“This ensures that a new instruction can be executed in every clock cycle, which eliminates wait states when no instruction is ready to be executed,” an Atmel engineering rep told Bits & Pieces. “The busses in AVR microcontrollers are configured to provide the CPU instruction bus priority access to the on-chip Flash memory. The CPU data bus has priority access to the SRAM.”

To make the AVR instruction set as efficient as possible, Atmel engineers invited compiler experts from IAR Systems to co-develop the first AVR C compiler. Following extensive refinement, the AVR architecture became optimized for C-code execution, with bottlenecks completely eliminated during the construction phase. This is why AVR has become synonymous with small code size, high performance and low power consumption.

“Usually, when the CPU executes a program, it requires frequent access to a limited set of data, including pointers, loop counters, semaphore status bits and array indexes. In fact, close inspection of source code will reveal that most of the data is only required for a very short amount of time, then later discarded,” the engineering rep explained. “That is why the AVR CPU contains multiple ‘working registers,’ which store dynamic data inside the CPU. Organized in a ‘register file,’ they eliminate the need to move temporary data from CPU to SRAM – only to read it back a few cycles later.”

To be sure, the register file is extremely fast, allowing the CPU to read, execute and store the result back into a register in a single clock cycle. They also require far less energy when accessed, compared to accessing a large SRAM with long address and data lines. Because no cycles are wasted, power consumption for executing code is greatly reduced.

In terms of DSP Instructions, the 32-bit AVR contains a very wide instruction set – with integer, fixed point and floating point DSP instructions – giving it the highest CPU performance of any AVR CPU.

“The 32-bit AVR instruction set also includes saturation and rounding instructions that help speed up loops by requiring no internal range check of intermediate results,” the engineering rep added. “With fast multiply, accumulate, and divide instructions, the 32-bit AVR is the perfect choice for applications that require extensive digital signal processing.”

Interested in learning more about Atmel’s 8- and 32-bit AVR portfolio? Check out our official product page here.