Two-Wire LIN networking with Atmel (Part 3)

In the first part of this series, we took a closer look at the basics of LIN networking, the key parameters for a two-wire LIN (Atmel) solution and the details of a LIN Bus power supply. In the second part of this series, we discussed various aspects of slave node current consumption, specifically, system clock frequency, sleep mode power management and LIN scheduling power management.

And today we’re going to talk about slave node buffer capacitance, LIN Bus data protocol and a multi-slave evaluation network.

“While an important piece of the two-wire LIN equation, sizing of the slave node buffer capacitor, CVS_S, is not a dominant factor. The capacitor must provide sufficient charge reserve to power the slave node during a LIN frame data packet (LIN signal is periodically asserted low) and also receive a full charge between LIN frame data transmissions (the LIN signal is pulled up to system supply voltage),” Atmel engineering rep Darius Rydahl told Bits & Pieces.

“In practice, bench tests indicate that a buffer capacitor of 47μF to 100μF is sufficient to maintain power to the slave node for a network operating at a data rate of 19.2kbaud with a 100ms delay (or greater) between LIN data frames and a 9V minimum operating battery voltage.”

In terms of the LIN Bus Data Protocol, Rydahl notes that the format of the LIN bus data protocol will affect the charge/discharge rate of the slave node supply line buffer capacitor. Three (primary) factors affect the data format: Rate of data transfer, quantity of data transferred and LIN data schedule table period.

“The LIN bus data rate should be kept high, i.e., a maximum baud rate of 19.2kHz or higher to maximize the speed at which the data can be transferred. The quantity of data number of bits) should be kept as low as possible in order to minimize the duration of the dominant state (logic level low) on the LIN bus line,” he continued.


“And finally, the LIN schedule table period should be long enough in duration to allow the LIN bus powered slave node time to fully recharge the buffer capacitor, CVS_S, between LIN message frames. It should also be noted that most Atmel LIN transceivers are capable of baud rates in excess of the LIN specification.”

On the multi-slave evaluation network side, the two-wire LIN network used for test and characterization purposes is illustrated in figure 8. Essentially, the two-wire LIN network total node count is limited only by the LIN master pull-up resistor’s ability to source the required current to the attached slave nodes to maintain normal operation (slave node VS greater than 5.5V).

“Each node has been configured using the Atmel ATA6617-EK evaluation board (SiP: AVR MCU, ATtiny167 and Atmel SBC ATA6624),” said Rydahl. “This configuration provides one possible operating scenario and, as such, will most likely need to be modified to accommodate the end user’s application.”

The network utilizes the standard LIN protocol and does not deviate from the LIN2.x standard in any manner. The schedule table has been optimized for the two-wire LIN application where a LIN wake-up frame is followed by a single slave node frame shown in figure 9.


“Standard LIN protocol dictates that each node must process every incoming frame ID message on the bus. This forces each slave node to wake-up on every incoming message, regardless of ownership. Sending a wake-up frame followed by a single slave node frame minimizes the time that each slave node is powered ON,” he added.

“The alternate approach of sending a wake-up frame followed by a sequential burst of all the slave frames will cause slave nodes to remain awake longer than necessary. The end result is an overall increase in system load current—a scenario that should be avoided.”

Interested in learning more about Two-Wire LIN networking with Atmel? Be sure to check out part one and two of this series. Part four will run tomorrow.

1 thought on “Two-Wire LIN networking with Atmel (Part 3)

  1. Pingback: Two-Wire LIN networking with Atmel (Part 4) | Bits & Pieces from the Embedded Design World

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